MCV

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System on Module featuring an Altera Cyclone V SoC FPGA

MCV offers the full flexibility of the Altera Cyclone V SoC FPGA family.  It integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The Altera SoCs combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic.

MCV features additional hard logic such as PCI Express® Gen1, multiport memory controllers, and high-speed serial transceivers. Our SoCs drive down power and cost while enabling performance levels required by cost-sensitive applications.

Due to the flexibility of the MCV concept  25KLE, 40KLE, 85KLE and 110KLE FPGAs are supported by MCV.

 


MCV Blockdiagram

 


MCV feature set

  • Altera Cyclone V SoC FPGA
    • without PCIe support
      • A2: 5CSEBA2U23C8N
        25KLE, 36 DSP blocks
      • A4: 5CSEBA4U23C8N
        40KLE, 58 DSP blocks
      • A5: 5CSEBA5U23C8N
        85KLE, 87 DSP blocks
      • A6: 5CSEBA6U23C8N
        110KLE, 112 DSP blocks
    • with PCIe support
      • A2: 5CSXFC2C6U23C7N
        25KLE, 36 DSP blocks, 6 transceivers 2.5Gbit/s
      • A4: 5CSXFC4C6U23C7N
        40KLE, 58 DSP blocks, 6 transceivers 2.5Gbit/s
      • A5: 5CSXFC5C6U23C7N
        85KLE, 87 DSP blocks, 6 transceivers 2.5Gbit/s
      • A6: 5CSXFC6C6U23C7N
        110KLE, 112 DSP blocks, 6 transceivers 2.5Gbit/s
  • Dual 800 MHz Cortex A9 Cores
  • HPS-Peripherals
  • 1 GByte DDR3-Speicher
  • 256 Mbit Coniguration Device
  • 4GByte eMMC memory
  • 143 FPGA signals
  • 66 HPS signals
  • Clock distribution
  • default configuration:
    • Gigabit Ethernet
    • UART
    • CAN
    • SPI
    • I²C
    • USB
  • additional interfaces would be optionally available such as
    • one or more display controller
    • second Gigabit Ethernet
    • CAN, SPI, I²C,
    • camera port
    • DSP blocks
    • microcontroller
  • single 3,3V supply
  • size 74mmx42mm
  • 2 x Samtec QSH-090-01-F-D-A board-to-board interconnect

Cyclone V SoC Hard Processor System

Altera SoCs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone.

SoC_HPS

Although the HPS and the FPGA can operate independently, they are tightly coupled via a high-bandwidth system interconnect built from high-performance ARM AMBA® AXITM bus bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS interconnect.


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